About the job
Google is making it easier for people to do things every day, whether it’s searching for photos of loved ones, breaking down language barriers in Google Translate, typing emails on the go, or getting things done with the Google Assistant. By focusing much of our research on machine learning and related techniques, we aim to provide new ways of looking at existing problems, from rethinking healthcare to advancing scientific discovery. Google Quantum AI constantly pushes performance boundaries by exploring novel chip fabrication as well as packaging approaches. This role will explore and implement a broad range of packaging techniques and the associated electrical, mechanical and reliability considerations. You will be working alongside other team members on the development and production of unique packaging solutions for the quantum hardware chips and PCBs. You will work closely with scientists and engineers in chip and package design to deliver packages with a unique set of requirements. In this role, you will help manage existing vendor supply chains and explore new vendors and manufacturing techniques to satisfy the growing demand by the entire Quantum Hardware team. In this role, you will help define standards and specifications, design tests of experiments, and perform failure analysis.
Responsibilities
Manage development of advanced packaging techniques for quantum hardware, including 3D integration, interconnects, multi-wafer integration, wirebonds, bumps, land grid array, thru-silicon vias, spring contacts, and micromachining
Manage, organize, prioritize, and maintain the interface for packaging as a service to other teams
Manage inventory, vendor supply chain, presenting design rules, defining interfaces between packaging and other teams (e.g., test, fabrication, design, etc.).
Review designs and troubleshoot issues with cross-functional teams
Develop specifications and reliability standards for complete package solutions
Minimum qualifications:
Bachelor's degree in Packaging Engineering, Mechanical/Electrical/Microelectronics Engineering, or equivalent practical experience
3 years of experience, with direct experience designing, developing, and testing for packaging techniques
Experience in conventional package techniques, including 3D integration, micromachining, and related inspection techniques to characterize
Experience with reliability assessment (e.g., operating environmental chambers, stress testing)
Preferred qualifications:
Master’s degree or PhD in Packaging Engineering, Mechanical/Electrical/Microelectronics Engineering, or Materials Science
Experience with packaging development for MEMS, sensors, or other non-semiconductor devices
Experience with failure analysis techniques
Experience building and managing vendor supply chain
Familiarity with PCB manufacturing processes
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